
Senior FPGA Design Engineer in Nashua, New Hampshire, United States
BAE · Capital Goods
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</br><b>Job Description </b></br><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma",sans-serif"=""><span style="color:#121212">BAE Systems has an open position for a Senior FPGA Digital Design Engineer!<br><br>See what you’re missing. Our employees work on the world’s most advanced electronics – from detecting threats for F-35 pilots to illuminating the night for soldiers. Spanning air, land, sea, and space, we are developing the technology of tomorrow, delivered today. Drawing strength from our differences, we’re innovating for the future. And you can, too. Our flexible work environment provides you a chance to change the world without giving up your personal life. We put our customers first – exemplified by our mission: “We Protect Those Who Protect Us®.” Sound like a team you want to be a part of? Come build your career with BAE Systems. </span></span></span></span></span><br><br><span style="font-size:10.5pt"><span style="line-height:107%"><span style="font-family:" tahoma",sans-serif"=""><span style="color:#121212"><span style="background:white"> <span style="border:none windowtext 1.0pt; padding:0in">At BAE Systems, we deliver a full range of products and services for air, land and naval forces, as well as advanced electronics, security, information technology solutions and customer support services. If you are an individual that enjoys a cohesive team environment and is interested in a variety of challenges across a variety of products, then we are interested in hearing from you!</span></span><br> <br><span style="border:none windowtext 1.0pt; background:white; padding:0in">Countermeasure & Electromagnetic Attack Solutions (CEMA) Hardware Engineering Group is looking for a Senior FPGA Digital Design Engineer to support FPGA designs through all phases of development.</span> <span style="border:none windowtext 1.0pt; background:white; padding:0in">The ideal candidate is expected to perform activities including assisting in design architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing, product support and FPGA security.</span></span></span></span></span></span></span></span><br></br></br><b>Required Education, Experience, & Skills </b></br><ul><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Current Security Clearance (Secret), or eligible to obtain one</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Typically 2 of years of relevant experience with bachelor’s degree, or equivalent experience</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience in FPGA or ASIC Design / Development, including</span></span></span></span></span></span></span></span><ul style="list-style-type:circle"><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list 1.0in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">VHDL (preferred) or Verilog HDL coding</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list 1.0in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience with digital design tools and simulators</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list 1.0in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience with clock domain crossing techniques</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list 1.0in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience with designer-level test bench (VHDL, Verilog, or SystemVerilog)</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list 1.0in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Familiarity with revision control (GIT, CVS, Clearcase, Subversion, etc.)</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list 1.0in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Familiarity with static timing analysis tools and timing closure</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list 1.0in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Working knowledge of internal logic analyzer (ILA/chipscope/signaltap)</span></span></span></span></span></span></span></span></li></ul></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Strong written and oral communication skills</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Self-starter and a good team player</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Ability to mentor and willingness to be mentored</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Strong debug and problem solving skills</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Lab testing support</span></span></span></span></span></span></span></span></li></ul></br></br><b>Preferred Education, Experience, & Skills </b></br><ul><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience with DSP fundamentals and FPGA implementation</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience with Matlab/Simulink</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience dealing with legacy designs</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience in hardware design and hands-on lab debug</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience with Xilinx Vivado or Intel/Altera Quartus</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience running digital simulations with Modelsim/QuestaSim</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Experience generating scripts (Perl, Tcl, Python, shell, etc.)</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Working knowledge of UVM/SystemVerilog</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Working knowledge of Radar systems</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Working knowledge of Video/IR processing systems</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Working knowledge of stepper motor control</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Working knowledge of C/C++</span></span></span></span></span></span></span></span></li><li><span style="font-size:11pt"><span style="background:white"><span style="color:#121212"><span style="line-height:normal"><span style="tab-stops:list .5in"><span style="font-family:Calibri,sans-serif"><span style="border:none windowtext 1.0pt; font-size:10.5pt; padding:0in"><span style="background:white">Working knowledge of high speed ADC/DAC interfaces, SERDES, PCIe</span></span></span></span></span></span></span></span></li></ul><br><br><b>Pay Information</b><br>Full-Time Salary Range: $79365 - $134921<br><br>Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience. <br><br>Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20+ hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.<br></br></br><b>About BAE Systems Electronic Systems </b></br>BAE Systems, Inc. is a defense, aerospace, and security company headquartered in Falls Church, Virginia, with more than 40,000 employees worldwide. We serve, supply, and protect those who protect us. As one of the most geographically diverse international defense companies, we deliver a full range of products and services spanning air, land, maritime, space, and cyber, including advanced electronics, intelligence solutions, and dedicated customer support.<br><br>Our culture is performance-driven and values-led, built on curiosity, creativity, and collaboration. Purpose isn't a tagline here. It's what drives us. We're developing breakthrough technologies that defend national security and make a lasting impact on our communities and our planet. When you join BAE Systems, you're not just building a career. You're contributing to a mission that truly matters.<br><br>This position will be posted for at least 5 calendar days. The posting will remain active until the position is filled, or a qualified pool of candidates is identified.