
FPGA Design Lead - Digital Signal Processing (DSP) in Nashua, New Hampshire, United States
BAE · Capital Goods
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</br><b>Job Description </b></br><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Electronic Combat Solutions Hardware Engineering Group is seeking a Senior Principal II FPGA Design Engineer to lead and develop a team of FPGA designer engineers through all phases of development. The ideal candidate is expected to perform activities including requirements generation and design architecture; technical oversight and mentoring of team members; as well as ownership of RTL coding, synthesis, basic test bench development, lab testing, and product support.<br><br>BAE offers competitive pay, benefits and important work-life balance initiatives including every other Friday off and flex time. BAE also believes in a culture of recognition for extraordinary contributions or our skilled employees.<br><br>Because of the need for consistent, in-person collaboration and the requirement to perform all work onsite due to the nature of this particular role, it will be performed full-time on site.<br><br>**Please not that pursuant to a government contract, along with the ability to obtain a minimum of Secret Clearance**</span></span></span></span></span><br><br></br></br><b>Required Education, Experience, & Skills </b></br><ul style="margin-bottom:11px"><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">10+ years of relevant experience with bachelor's degree (less with an advanced degree)</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Current Security Clearance (Secret), or eligible to obtain one</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Ability to distill higher level requirements into micro-architecture</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Extensive experience in FPGA (preferred) or ASIC Design / Development</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience leading/managing a design team</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience with DSP fundamentals</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Working understanding of Radar systems and/or EW systems</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Proficient in VHDL (preferred) or Verilog HDL coding</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Familiarity with Xilinx Vivado/ISE or Altera Quartus</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Digital simulation using Modelsim/Questa</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Strong understanding of timing driven design including clock domain crossing circuitry</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Strong lab debug and problem solving skills</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Strong written and oral communication skills</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Ability to mentor and willingness to be mentored</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience with high-speed interfaces like PCIe, SerDes, ADC/DAC, DDR3/4</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Familiarity with revision control (GIT, CVS, Clearcase, Subversion, etc.)</span></span></span></span></span></span></span></span></li><li style="margin-bottom:11px; margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Proficient in Tcl/Tk and UNIX/Linux shell programming</span></span></span></span></span></span></span></span></li></ul></br></br><b>Preferred Education, Experience, & Skills </b></br><ul style="margin-bottom:11px"><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience with FPGA implementation</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience with Matlab/Simulink</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience creating unique designs and supporting legacy designs</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience with UVM/System Verilog</span></span></span></span></span></span></span></span></li><li style="margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Some experience with managing schedule and cost is beneficial</span></span></span></span></span></span></span></span></li><li style="margin-bottom:11px; margin-left:8px"><span style="font-size:11pt"><span style="line-height:107%"><span style="font-family:Calibri,sans-serif"><span style="font-size:10.5pt"><span style="background:white"><span style="line-height:107%"><span style="font-family:" tahoma=""><span style="color:#121212">Experience with C/C++, Perl and Python</span></span></span></span></span></span></span></span></li></ul><br><br><b>Pay Information</b><br>Full-Time Salary Range: $149603 - $254317<br><br>Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience. <br><br>Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20+ hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.<br></br></br><b>About BAE Systems, Inc.</b></br>BAE Systems, Inc. is a defense, aerospace, and security company headquartered in Falls Church, Virginia, with more than 40,000 employees worldwide. We serve, supply, and protect those who protect us. As one of the most geographically diverse international defense companies, we deliver a full range of products and services spanning air, land, maritime, space, and cyber, including advanced electronics, intelligence solutions, and dedicated customer support.<br><br>Our culture is performance-driven and values-led, built on curiosity, creativity, and collaboration. Purpose isn't a tagline here. It's what drives us. We're developing breakthrough technologies that defend national security and make a lasting impact on our communities and our planet. When you join BAE Systems, you're not just building a career. You're contributing to a mission that truly matters.<br><br>This position will be posted for at least 5 calendar days. The posting will remain active until the position is filled, or a qualified pool of candidates is identified.