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FPGA Design Engineer, Senior Principal in Nashua, New Hampshire, United States

BAE · Capital Goods
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</br><b>Job Description </b></br><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Be part of a new age where firmware and digital design shape technological advantages on the battlefield. Help empower pilots, soldiers, and operators by developing mission‑critical systems that deliver stealth, protection, and next‑generation electronic capabilities. Join the team that protects those who protect us—at BAE Systems.</span></span></span><br><br><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">We are seeking a Sr. Principal FPGA Digital Design Engineer who brings strong technical leadership, initiative, and a drive to push the boundaries of what’s possible. In this role, you will work cross‑functionally with hardware, software, and systems engineering teams, taking full ownership of high‑impact design challenges from concept through delivery, and contributing innovative solutions to problems many consider unsolvable.</span></span></span><br><br><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">BAE Systems offers a modern, flexible work environment that supports work‑life balance—including a 9‑days/80‑hours pay period—and a mission‑focused culture where every design delivers real‑world impact.</span></span></span><h1 style="margin-top:24px; margin-bottom:5px"><span style="font-size:20pt"><span style="line-height:115%"><span style="font-family:" aptos="" display",sans-serif"=""><span style="color:#0f4761"><span style="font-weight:normal">Role Responsibilities</span></span></span></span></span></h1><ul><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Support program proposal development by defining technical solutions, estimating effort and budget, and collaborating with systems, hardware, and software teams to align with customer requirements.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Serve as an expert in advanced digital, FPGA, and system<span style="font-family:" cambria="" math",serif"="">‑</span>level design by contributing to research initiatives that develop leading<span style="font-family:" cambria="" math",serif"="">‑</span>edge concepts and establish new engineering platform solutions. </span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Translate FPGA design requirements from system‑level inputs in close collaboration with hardware, systems, and software teams to ensure seamless FPGA performance and integration.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Architect and implement FPGA designs across major device families (Xilinx, Intel, Microchip, Lattice) using VHDL, supporting applications ranging from gigabit‑rate serial links and RF DSP to control loops, embedded processing, and processor‑level interfaces.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Innovate with next‑generation FPGA platforms (Xilinx Zynq SoC, RFSoC), use SystemVerilog, UVM, and digital‑twin co‑simulation methodologies.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Drive synthesis, place‑and‑route, static timing analysis, and overall design optimization.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Build high‑quality test benches, simulation environments, and static verification setups (Lint, Autocheck, CDC, RDC).</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Lead hands‑on lab integration, perform daily real‑time testing, and incorporate direct feedback from flight test operations and end users.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Support development workflows and participate in formal specification and design reviews.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Manage version control and configuration processes using Git/GitLab while maintaining accurate, up‑to‑date design documentation.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Serve as a mentor to senior and junior design engineers and help strengthen overall team technical capability.</span></span></span></li><li style="margin-left:8px"><span style="font-size:12pt"><span style="line-height:15.0pt"><span style="font-family:Aptos,sans-serif">Maintain full awareness of program schedules and budgets.</span></span></span></li></ul></br></br><b>Required Education, Experience, & Skills </b></br><ul style="margin-bottom:11px"><li class="MsoListBulletCxSpFirst"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">BS degree in Electrical Engineering or related Science, Technology, Engineering and Mathematics (STEM) major obtained by start date.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">8+ years VHDL/Verilog expertise. </span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Expertise in developing advanced concepts and innovative technical solutions.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Expertise in clock domain crossing, timing analysis, revision control.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Experience in hardware-software integration and validation.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Familiarity with Xilinx, Intel, Microchip or Lattice devices and tool flows. </span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Familiarity with the Linux environment and commands. </span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Knowledge of C programming and scripting languages such as Perl, Tcl and Python. </span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Demonstrated effective communication, collaboration, and presentation skills</span></span></span></span></li><li class="MsoListBulletCxSpLast" style="margin-bottom:11px"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Must be a U.S. Citizen; must be able to obtain/maintain a DoD Secret clearance</span></span></span></span></li></ul></br></br><b>Preferred Education, Experience, & Skills </b></br><ul style="margin-bottom:11px"><li class="MsoListBulletCxSpFirst"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Advance knowledge of Digital Signal Processing</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Experience with architecture design in Matlab/Simulink.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Experience with platforms as Vivado and Modelsim/QuestaSim.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Experience with UVM/SystemVerilog, hardware debug.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Experience with High-speed interfaces (PCIe).</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Proficiency in a Linux development environment.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Proficiency using Git and CI/CD workflows.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Knowledge of software programming languages such as C/ C++.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric, and IP.</span></span></span></span></li><li class="MsoListBulletCxSpMiddle"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Previous experience related to aerospace design techniques.</span></span></span></span></li><li class="MsoListBulletCxSpLast" style="margin-bottom:11px"><span style="font-size:12pt"><span style="tab-stops:list .25in"><span style="line-height:115%"><span style="font-family:Aptos,sans-serif">Active DoD Secret or Top Secret clearance.</span></span></span></span></li></ul><br><br><b>Pay Information</b><br>Full-Time Salary Range: $132962 - $226035<br><br>Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience. <br><br>Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20+ hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.<br></br></br><b>About BAE Systems, Inc.</b></br>BAE Systems, Inc. is a defense, aerospace, and security company headquartered in Falls Church, Virginia, with more than 40,000 employees worldwide. We serve, supply, and protect those who protect us. As one of the most geographically diverse international defense companies, we deliver a full range of products and services spanning air, land, maritime, space, and cyber, including advanced electronics, intelligence solutions, and dedicated customer support.<br><br>Our culture is performance-driven and values-led, built on curiosity, creativity, and collaboration. Purpose isn't a tagline here. It's what drives us. We're developing breakthrough technologies that defend national security and make a lasting impact on our communities and our planet. When you join BAE Systems, you're not just building a career. You're contributing to a mission that truly matters.<br><br>This position will be posted for at least 5 calendar days. The posting will remain active until the position is filled, or a qualified pool of candidates is identified.